Latitude 7490: patching for TB3 ports

tinDell · April 7, 2022

On 2/10/2022 at 8:05 AM, Baio77 said:

https://drive.google.com/drive/folders/1WFRVB2CHSM_xYcUXEeQoaUblyPcdjJ7o?usp=sharing test this EFI if start ioreg .
You should let them know if your Dell has integrated TB3 ports. In case patches need to be added.

How to patch? Mine with TB3

Baio77 · April 8, 2022

You probably need an ACPI + Kext patch or driver, it depends on the TB3 version you have .... Activating this device most likely interferes with sleep \ wake.
Post ioreg your hack.

tinDell · April 9, 2022

Here is my ioreg.

mac’s ioreg.zip

Baio77 · April 9, 2022

From ioreg I don't see the TB3, but it should be staying on RP05. In Bios you have active the options for TB3 ??

Test this EFI ioreg if start https://drive.google.com/drive/folders/1WFRVB2CHSM_xYcUXEeQoaUblyPcdjJ7o?usp=sharing

tinDell · April 10, 2022

It was activated

tinDell · April 11, 2022

Before using your EFI in system information, Thunderbolt: no hardware found. After: no drivers are loaded.

As you said, now wake from sleep take a little longer than before. Just now even failed to wake. I will try to use my previous SSDT files. Here is the ioreg.

Edit: Proven. Use your SSDT made wake time response longer or failed sometimes. Now I keep the previous.

mac’s ioreg.zip

Baio77 · April 11, 2022

In ioreg RP05 you see the TB3, but it still doesn't work, you need an SSDT-TB3 for that TB3 model.

tinDell · April 13, 2022

Not yet search for SSDT-TB3. Just report that try to activate thunderbolt made display port function sometimes failed.

Baio77 · April 13, 2022

Quote

If (_OSI ("Darwin"))
{
Scope (RP05)
{
Scope (PXSX)
{
Name (_STA, Zero) // _STA: Status
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}

Device (UPSB)
{
Name (_ADR, Zero) // _ADR: Address
OperationRegion (A1E0, PCI_Config, Zero, 0x40)
Field (A1E0, ByteAcc, NoLock, Preserve)
{
AVND, 32,
BMIE, 3,
Offset (0x18),
PRIB, 8,
SECB, 8,
SUBB, 8,
Offset (0x1E),
, 13,
MABT, 1
}

Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x03
})
}

Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number
{
Return (SECB) /* \_SB_.PCI0.RP05.UPSB.SECB */
}

Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}

Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x06)
{
"AAPL,slot-name",
Buffer (0x07)
{
"Slot-4"
},

"built-in",
Buffer (One)
{
0x00 // .
},

"PCI-Thunderbolt",
One
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}

Device (DSB0)
{
Name (_ADR, Zero) // _ADR: Address
OperationRegion (A1E0, PCI_Config, Zero, 0x40)
Field (A1E0, ByteAcc, NoLock, Preserve)
{
AVND, 32,
BMIE, 3,
Offset (0x18),
PRIB, 8,
SECB, 8,
SUBB, 8,
Offset (0x1E),
, 13,
MABT, 1
}

Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}

Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x03
})
}

Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number
{
Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB0.SECB */
}

Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x06)
{
"AAPL,slot-name",
Buffer (0x07)
{
"Slot-4"
},

"built-in",
Buffer (One)
{
0x00 // .
},

"PCIHotplugCapable",
Zero
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}

Device (NHI0)
{
Name (_ADR, Zero) // _ADR: Address
Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}

Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x03
})
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}

Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x11)
{
"AAPL,slot-name",
Buffer (0x07)
{
"Slot-4"
},

"name",
Buffer (0x24)
{
"Alpine Ridge Thunderbolt Controller"
},

"model",
Buffer (0x2D)
{
"Intel JHL6540 Alpine Ridge Thunderbolt 3 NHI"
},

"device_type",
Buffer (0x17)
{
"Thunderbolt-Controller"
},

"ThunderboltDROM",
Buffer (0x77)
{
/* 0000 */ 0x02, 0x00, 0xD2, 0x05, 0x31, 0xB4, 0x1E, 0x81, // ....1...
/* 0008 */ 0xBB, 0x9C, 0xE1, 0x7F, 0xFF, 0x01, 0x6A, 0x00, // ......j.
/* 0010 */ 0x01, 0x00, 0x0D, 0x00, 0x01, 0x00, 0x08, 0x81, // ........
/* 0018 */ 0x80, 0x02, 0x80, 0x00, 0x00, 0x00, 0x08, 0x82, // ........
/* 0020 */ 0x90, 0x01, 0x80, 0x00, 0x00, 0x00, 0x08, 0x83, // ........
/* 0028 */ 0x80, 0x04, 0x80, 0x01, 0x00, 0x00, 0x08, 0x84, // ........
/* 0030 */ 0x90, 0x03, 0x80, 0x01, 0x00, 0x00, 0x02, 0x85, // ........
/* 0038 */ 0x0B, 0x86, 0x20, 0x01, 0x00, 0x64, 0x00, 0x00, // .. ..d..
/* 0040 */ 0x00, 0x00, 0x00, 0x03, 0x87, 0x80, 0x05, 0x88, // ........
/* 0048 */ 0x50, 0x40, 0x00, 0x05, 0x89, 0x50, 0x00, 0x00, // [email protected]..
/* 0050 */ 0x05, 0x8A, 0x50, 0x00, 0x00, 0x05, 0x8B, 0x50, // ..P....P
/* 0058 */ 0x40, 0x00, 0x0B, 0x01, 0x47, 0x49, 0x47, 0x41, // @...GIGA
/* 0060 */ 0x42, 0x59, 0x54, 0x45, 0x00, 0x12, 0x02, 0x47, // BYTE...G
/* 0068 */ 0x43, 0x2D, 0x41, 0x6C, 0x70, 0x69, 0x6E, 0x65, // C-Alpine
/* 0070 */ 0x20, 0x52, 0x69, 0x64, 0x67, 0x65, 0x00 // Ridge.
},

"ThunderboltConfig",
Buffer (0x20)
{
/* 0000 */ 0x00, 0x02, 0x1C, 0x00, 0x02, 0x00, 0x05, 0x03, // ........
/* 0008 */ 0x01, 0x00, 0x04, 0x00, 0x05, 0x03, 0x02, 0x00, // ........
/* 0010 */ 0x03, 0x00, 0x05, 0x03, 0x01, 0x00, 0x00, 0x00, // ........
/* 0018 */ 0x03, 0x03, 0x02, 0x00, 0x01, 0x00, 0x02, 0x00 // ........
},

"linkDetails",
Buffer (0x08)
{
0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00 // ........
},

"power-save",
One,
Buffer (One)
{
0x00 // .
}
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}
}
}

Device (DSB1)
{
Name (_ADR, 0x00010000) // _ADR: Address
OperationRegion (A1E0, PCI_Config, Zero, 0x40)
Field (A1E0, ByteAcc, NoLock, Preserve)
{
AVND, 32,
BMIE, 3,
Offset (0x18),
PRIB, 8,
SECB, 8,
SUBB, 8,
Offset (0x1E),
, 13,
MABT, 1
}

Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x03
})
}

Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number
{
Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.SECB */
}

Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}
}

Device (DSB2)
{
Name (_ADR, 0x00020000) // _ADR: Address
OperationRegion (A1E0, PCI_Config, Zero, 0x40)
Field (A1E0, ByteAcc, NoLock, Preserve)
{
AVND, 32,
BMIE, 3,
Offset (0x18),
PRIB, 8,
SECB, 8,
SUBB, 8,
Offset (0x1E),
, 13,
MABT, 1
}

Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x03
})
}

Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number
{
Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB2.SECB */
}

Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (One)
}

Device (XHC2)
{
Name (_ADR, Zero) // _ADR: Address
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}

Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}

Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x18)
{
"AAPL,slot-name",
Buffer (0x07)
{
"Slot-4"
},

"built-in",
Buffer (One)
{
0x00 // .
},

"name",
Buffer (0x20)
{
"Alpine Ridge USB 3.1 Controller"
},

"model",
Buffer (0x23)
{
"Intel JHL6540 Alpine Ridge USB 3.1"
},

"device_type",
Buffer (0x1F)
{
"USB eXtensible Host-Controller"
},

"AAPL,current-available",
0x0834,
"AAPL,current-extra",
0x0A8C,
"AAPL,current-in-sleep",
0x0A8C,
"AAPL,max-port-current-in-sleep",
0x0834,
"AAPL,device-internal",
Zero,
"AAPL,root-hub-depth",
0x1A,
"AAPL,XHC-clock-id",
One
}
DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0))
Return (Local0)
}

Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake
{
Return (Package (0x02)
{
0x69,
0x03
})
}

Device (RHUB)
{
Name (_ADR, Zero) // _ADR: Address
Method (_RMV, 0, NotSerialized) // _RMV: Removal Status
{
Return (Zero)
}

Device (HS01)
{
Name (_ADR, One) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)

})
}

Device (HS02)
{
Name (_ADR, 0x02) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)

})
}

Device (SSP1)
{
Name (_ADR, 0x03) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)

})
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x03 // .
})
}

Return (Package (0x04)
{
"UsbCPortNumber",
One,
"UsbPowerSource",
One
})
}
}

Device (SSP2)
{
Name (_ADR, 0x04) // _ADR: Address
Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities
{
0xFF,
0x09,
Zero,
Zero
})
Name (_PLD, Package (0x01) // _PLD: Physical Location of Device
{
ToPLD (
PLD_Revision = 0x1,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "UPPER",
PLD_HorizontalPosition = "LEFT",
PLD_Shape = "UNKNOWN",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)

})
Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
{
If ((Arg2 == Zero))
{
Return (Buffer (One)
{
0x03 // .
})
}

Return (Package (0x04)
{
"UsbCPortNumber",
0x02,
"UsbPowerSource",
0x02
})
}
}
}
}
}
}
}
}

Example SSDT TB3 Dell 7390 CPU Kabylake -R

tinDell · April 15, 2022

Thanks, but I think to postpone for a while. Wake function not working at all when I used the kext and driver.

Sign In

Latitude 7490: patching for TB3 ports

Recommended Posts

tinDell

Link to comment

Share on other sites

Baio77

Link to comment

Share on other sites

tinDell

Link to comment

Share on other sites

Baio77

Link to comment

Share on other sites

tinDell

Link to comment

Share on other sites

tinDell

Link to comment

Share on other sites

Baio77

Link to comment

Share on other sites

tinDell

Link to comment

Share on other sites

Baio77

Link to comment

Share on other sites

tinDell

Link to comment

Share on other sites

Categories

OSXLatitude

Installation Guides

Help & Support

Browse